AMD published details on Sunday outlining how its programmable network interface card architecture handles multiple high-speed Ethernet transports for artificial intelligence workloads. The design focuses on processing heavy cluster traffic across several transport protocols rather than tying network hardware to a single standard.
The company shared the technical outline in an October 11 blog post. According to the release, the programmable architecture specifically accommodates transports defined by the Ultra Ethernet Consortium, alongside Multipath Reliable Connection and MetaRoCE protocols.
Transport options across AI clusters
AI clusters rely on high-bandwidth network pipelines to transfer data between hardware nodes during intensive computing runs. Different data centers implement distinct communication protocols to manage those data flows, creating varying demands on the network interface cards installed in individual servers.
AMD's design addresses this protocol variance directly at the network interface layer. By making the AI NIC architecture fully programmable, the hardware can accept and process traffic running on multiple Ethernet transports instead of demanding fixed, protocol-specific silicon configurations.
Support for three Ethernet protocols
The architecture targets three distinct networking specifications commonly used or developed for distributed AI setups. The first is transport specification work coming out of the Ultra Ethernet Consortium, an effort centered on tailoring Ethernet for high-demand scale-out architectures.
Along with Ultra Ethernet Consortium transport handling, the programmable hardware accommodates Multipath Reliable Connection. The architecture also integrates support for MetaRoCE transports. By housing these capabilities on a single programmable framework, the setup allows data centers to deploy network cards across varied networking configurations without retooling their core underlying hardware.
Programmability for specialized compute
Hardware programmability forms the foundation of the architecture. Instead of running on rigid paths, the AI NIC uses a flexible processing pipeline capable of adapting to workload characteristics and differing transport layer requirements.
Large distributed workloads place unique pressures on data flow management and cluster communication. The design aims to maintain stability across these transfers by keeping packet handling adaptable to the specific transport protocol in use across the cluster fabric.
Deployment across AI workloads
AMD designed the architecture exclusively around the requirements of artificial intelligence tasks. Distributed training, data synchronization, and large-scale model inference rely on consistent, reliable data movement across thousands of interconnected chips, making network efficiency critical to compute performance.
The company has laid out the core architecture across Ultra Ethernet Consortium, Multipath Reliable Connection, and MetaRoCE protocols. The practical implementation of these transports will depend on how network operators integrate the programmable cards into their active AI cluster architectures.
