Samsung, Micron, and SK hynix are scrapping their internal development of CXL memory controllers. The three memory giants are instead outsourcing the work to fabless chip designers like Primemas, as timelines for the CXL 3.x standard slip.
Why the CXL Controller Pivot
Compute Express Link, or CXL, is a high-speed interconnect that lets CPUs, memory, and accelerators share data more efficiently. The technology is central to next-generation data center architectures, especially for AI and large-scale computing. But the latest version, CXL 3.x, has taken longer than expected to finalize. That delay has made it harder for Samsung, Micron, and SK hynix to justify the cost and engineering resources needed to build their own controllers in-house.
Instead, they're turning to specialized fabless firms that focus solely on CXL controller design. Primemas, a Taiwan-based company, is one of the beneficiaries. The shift means the memory makers will buy off-the-shelf controllers rather than develop proprietary ones.
What CXL 3.x Delays Mean for the Industry
CXL 3.x was supposed to bring major improvements in memory pooling and sharing. But the standard's ratification has dragged on, pushing back product roadmaps. For Samsung, Micron, and SK Hynix, that uncertainty made internal development a risky bet. By outsourcing, they can adapt more quickly once the standard firms up.
The move also signals a broader trend: memory companies are increasingly relying on third-party chip designers for complex logic components. It's a shift from the vertically integrated model that has long defined the memory industry.
The Role of Fabless Firms
Primemas isn't the only fabless company getting attention. Others in the CXL controller space include Astera Labs and Rambus. But Primemas appears to be the primary partner for the three memory makers. The company already has experience with CXL 2.0 controllers and is working on 3.x designs.
For the fabless firms, this is a major opportunity. They get to supply controllers to the three companies that dominate the global memory market. But they also face pressure to deliver chips that meet the performance and reliability standards of hyperscale data center customers.
The memory makers haven't said when they expect to have CXL 3.x products using the new controllers. That timeline depends on when the standard is finalized and how quickly the fabless firms can tape out working silicon.
