The CEO of Taiwan Semiconductor Manufacturing Co. is laying out a plan to make High-NA EUV lithography more cost-effective, even as the company proceeds with a cautious adoption strategy for the next-generation chipmaking technology. The dual approach reflects the steep financial and strategic challenges that High-NA EUV presents not just for TSMC but for the entire semiconductor industry.
The cost premium of High-NA EUV
High-NA EUV (high numerical aperture extreme ultraviolet) lithography is widely seen as essential for continuing Moore's Law at the most advanced nodes. But the machines, built by Dutch supplier ASML, carry a price tag that runs into hundreds of millions of dollars each. Installation, infrastructure upgrades, and maintenance costs push the total investment even higher. TSMC's CEO has been detailing efforts to improve the technology's cost-effectiveness, signaling that the company wants the benefits of finer patterning without absorbing the full financial burden.
Why TSMC isn't rushing
Despite the potential advantages, TSMC is moving deliberately. The company has not committed to a rapid, widespread rollout of High-NA EUV in its upcoming process nodes. Instead, it is evaluating when and where the technology makes economic sense. Industry observers note that TSMC's careful pace contrasts with the more aggressive timelines some analysts had expected. The strategy suggests that TSMC intends to squeeze more life from existing EUV systems before shifting to the far more expensive High-NA generation.
Financial and strategic hurdles for chipmakers
The challenges are not unique to TSMC. All foundries and integrated device manufacturers chasing the leading edge face the same calculus: High-NA EUV can deliver smaller, more power-efficient transistors, but the return on investment is uncertain at a time when chip prices are under pressure. TSMC's cautious stance may also be a hedge against potential delays in High-NA tool availability or yields. By signaling that it can wait, TSMC puts pressure on ASML and on its own rivals — if competitors rush in and struggle with costs, TSMC could gain a long-term advantage.
The company's approach leaves open questions about the exact timeline for first use of High-NA EUV in volume manufacturing. TSMC has not yet said which process node will be the first to rely on the technology, or how many High-NA tools it will eventually install. Those decisions will likely depend on how quickly the cost-efficiency initiatives outlined by the CEO can be realized in practice.
